The present invention relates to a memory circuit and more particularly to a dual port memory circuit.
Random access memories (RAMs) utilizing the LSI technique have been used mainly as the main memories of computers and have come into widespread use in office automation devices, such as personal computers. Due to the remarkable reduction in the cost per bit of storage, MOS random access memories are used for processing video images, especially for displaying images on a CRT. A memory device used with such a display is connected between a CPU and the CRT. However, conventional RAMs are inefficient for display applications. During the display period, the data is sent to the CRT continuously at a high speed data rate such as 45 ns. During this period, the RAM cannot exchange data with the CPU so that the CPU can neither rewrite nor read the content of the RAM. The data exchange between the RAM and the CPU is limited to the blanking period during which no image is displayed on the CRT. As a result, the CPU and the system efficiency is remarkably low.
It has been proposed that RAMs having an input/output system for a CPU and an output system for a CRT are the best suitable for display use. Such RAMs are called "dual port memory".
A known dual port memory is structured such that a serial access port is provided to the known RAM and a serial read operation to the CRT is performed via the serial access port while performing the usual random access operation by the commonly provided random input/output port. The serial access port includes a data register circuit for holding a plurality of data bits, a data transfer circuit for operatively applying a plurality of data bits stored in the selected row of the memory array to the data register circuit, and a serial selection circuit for serially selecting the data bits stored in the data register circuit.
However, the data transfer from the memory array to the data register circuit through the data transfer circuit must be performed in synchronism with the operation of the random access port. Furthermore, such data transfer necessitates a certain time period, and therefore serial access operations over the plurality of rows selected in sequence cannot be achieved at a high speed.